CPLD: Unterschied zwischen den Versionen
Tw (Diskussion | Beiträge) (→CPLD Boards) |
Tw (Diskussion | Beiträge) (→CPLD Boards) |
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| Zeile 3: | Zeile 3: | ||
*[[CPLD/8 Bit Baby|8 Bit Baby]] | *[[CPLD/8 Bit Baby|8 Bit Baby]] | ||
| − | *[[CPLD/Pollin|Pollin CPLD Board]] | + | *[[CPLD/Pollin|Pollin CPLD Board]] (XC95144XL + 128K SRAM) |
*[[CPLD/XC9572XL|Xilinx XC9572XL Board]] | *[[CPLD/XC9572XL|Xilinx XC9572XL Board]] | ||
*[[CPLD/OpenEPM1270|WaveShare Open-EPM1270]] | *[[CPLD/OpenEPM1270|WaveShare Open-EPM1270]] | ||
Version vom 17. September 2019, 00:19 Uhr
CPLD Boards
- 8 Bit Baby
- Pollin CPLD Board (XC95144XL + 128K SRAM)
- Xilinx XC9572XL Board
- WaveShare Open-EPM1270
